SF Memory

Independent semiconductor research lab in San Francisco.

Advanced manufacturing, packaging, and integration research for HBM3E, HBM4, stacked DRAM, and emerging 3D DRAM architectures.

Research topics:

• Vertical interconnects: TSV formation and reveal.
• Stack assembly: wafer thinning, known-good-die selection, fine-pitch micro-bumps, and molded underfill.
• Package integration: base-die interfaces, RDL interposers, thermal paths, and stack-level test.
• Process limits: warpage, thermal-mechanical reliability, signal and power integrity, compound yield, and manufacturability.

We also evaluate die-to-wafer copper hybrid bonding as a future interconnect path.